View LH28F008SCT-L12_1356731.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? integrated circuits group lh 28 f 008 sc t -l 12 fla sh me mor y 8 m ( 1 m 8 ) (model no.: lh f 08 ch 3 ) spec no.: el 10 4 1 64 b issue date: may 7 , 19 99 p roduc t s pecific a tions
sharp lhf08ch3 l handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). *office electronics *instrumentation and measuring equipment *machine tools @audiovisual equipment *home appliance *communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands hiqh reliabilitv, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. &ontrol and safety devices for airplanes, trains, automobiles, and other transportation equipment l mainframe computers l traffic control systems *gas leak detectors and automatic cutoff devices *rescue and security equipment mother safety devices and safety equipment,etc. (3) do not use the products covered herein for the following equipment which demands extremelv hiqh performance in terms of functionality, reliability, or accuracy. l aerospace equipment *communications equipment for trunk lines *control equipment for the nuclear power industry @medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. l please direct all queries regarding the products covered herein to a sales representative of the company. paw i 1
shari= lhf08ch3 1 contents page page 1.0 introduction ................................................... 3 1.1 new features.. .................................................... 3 1.2 product overview ................................................ 3 2.0 principles of operation.. ........................... 7 2.1 data protection ................................................... 7 3.0 bus operation ................................................. a 3.1 read ................................................................... a 3.2 output disable .................................................... 6 3.3 standby ............................................................... a 3.4 deep power-down .............................................. 8 3.5 read identifier codes operation.. ....................... 9 3.6 write .................................................................... 9 5.0 design considerations ............................. .23 5.1 three-line output control ................................ .23 5.2 ry/by# and block erase, byte write and lock-bit configuration polling.. ......................................... 23 5.3 power supply decoupling.. ................................ 23 5.4 v,, trace on printed circuit boards.. ............... .23 5.5 v,,, v,,, rp# transitions.. .............................. .24 5.6 power-up/down protection.. ............................. .24 5.7 power dissipation .............................................. 24 4.0 command definitions .................................... 9 4.1 read array command.. ..................................... 12 4.2 read identifier codes command ...................... 12 4.3 read status register command.. ..................... 12 4.4 clear status register command.. ..................... 12 4.5 block erase command.. .................................... 12 4.6 byte write command ........................................ 13 4.7 block erase suspend command.. ..................... 13 4.6 byte write suspend command.. ....................... 14 4.9 set block and master lock-bit commands.. ..... 14 4.10 clear block lock-bits command.. ................... 15 6.0 electrical specifications.. ..................... .25 6.1 absolute maximum ratings ............................... 25 6.2 operating conditions ......................................... 25 6.2.1 capacitance ................................................. 25 6.2.2 ac input/output test conditions.. ............... .26 6.2.3 dc characteristics ........................................ 27 6.2.4 ac characteristics - read-only operations .29 6.2.5 ac characteristics - write operations.. ....... .32 6.2.6 alternative ce#-controlled writes.. ............. .35 6.2.7 reset operations ......................................... 36 6.2.6 block erase, byte write and lock-bit configuration performance ........................... 39 7.0 additional information ............................ .40 7.1 ordering information ......................................... .40 8.0 package and packing specifications ..4 1 rev. 1.0
shai?p lhf08ch3 2 lh28foossct-l12 8m-bit (1 mb x 8) smartvoltage flash memory n smartvoltage technology - 2.7v(read-only), 3.3v or 5v vcc - 3.3v, 5v or 12v vpp n high-performance read access time - 120ns(5v*0.5v), 150ns(3.3v*o.3v), 170ns(2.7v-3.6v) n operating temperature - 0c to +7o?c i high-density symmetrically-blocked architecture - sixteen 64k-byte erasable blocks i low power management - deep power-down mode - automatic power savings mode decreases ice in static mode i enhanced data protection features - absolute protection with vpp=gnd - flexible block locking - block erase/byte write lockout during power transitions n automated byte write and block erase - command user interface - status register n enhanced automated suspend options - byte write suspend to read - block erase suspend to byte write - block erase suspend to read n extended cycling capability - 100,000 block erase cycles - 1.6 million block erase cycles/chip n sram-compatible write interface n industry-standard packaging - 40-lead tsop n etoxtm* nonvolatile flash techno wy w cmos process (p-type silicon substrate) n not designed or rated as radiation hardened sharp?s LH28F008SCT-L12 flash memory with smartvoltage technology is a high-density, low-cost, nonvolatile, ?ead/write storage solution for a wide range of applications. its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, slmms and memory :ards. its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the LH28F008SCT-L12 offers three levels of protection: absolute protection with v,, at znd, selective hardware block locking, or flexible software block locking. these alternatives give designers jltimate control of their code security needs. the LH28F008SCT-L12 is manufactured on sharp?s 0.38um etoxtm process technology. it come in ndustry-standard package: the 40-lead tsop, ideal for board constrained applications. based on the 28f008sa architecture, the LH28F008SCT-L12 enables quick and easy upgrades for designs demanding the state-of-the-art. ?etox is a trademark of intel corporation. rev. 1.3
lhf08ch3 3 1 introduction this datasheet contains LH28F008SCT-L12 specifications. section 1 provides a flash memory overview. sections 2, 3, 4, and 5 describe the memory organization and functionality. section 6 covers electrical specifications. LH28F008SCT-L12 flash memory documentation also includes application notes and design tools which are referenced in section 7. 1.1 new features the LH28F008SCT-L12 smartvoltage flash memory maintains backwards-compatibility with sharp?s 28f008sa. key enhancements over the 28f008sa include: *smartvoltage technology *enhanced suspend capabilities &r-system block locking both devices share a compatible pinout, status register, and software command set. these similarities enable a clean upgrade from the 28f008sa to LH28F008SCT-L12. when upgrading, it is important to note the following differences: *because of new feature support, the two devices have different device codes. this allows for software optimization. l vpplk has been lowered from 6.5v to l.5v to support 3.3v and 5v block erase, byte write, and lock-bit configuration operations. the v,, voltage transitions to gnd is recommended for designs that switch v,, off during read operation. *to take advantage of smartvoltage technology, allow v,, connection to 3.3v or 5v. 1.2 product overview the LH28F008SCT-L12 is a high-performance 8m-bit smartvoltage flash memory organized as 1 m-byte of 3 bits. the im-byte of data is arranged in sixteen sk-byte blocks which are individually erasable, ockable, and unlockable in-system. the memory nap is shown in figure 3. smartvoltage technology provides a choice of voc and v,, combinations, as shown in table 1, to mee system performance and power expectations. 2.7\ v,, consumes approximately one-fifth the power o 5v vo,. but, 5v vco provides the highest reac performance. v,, at 3.3v and 5v eliminates the neec for a separate 12v converter, while v,,=12\ maximizes block erase and byte write performance in addition to flexible erase and program voltages the dedicated v,, pin gives complete data protectior when v,+v,,,,. table 1. vc, and v,, voltage combinations offered by smartvoltage technology vr.r: voltage vpp voltage 2.7v(?) - -.. 3.3v 3.3v, 54, l2v 5v 5v. 12v i note: 1. block erase, byte write and lock-bit configuratior operations with v,o<3.ov are not supported. internal vcc and vp, detection circuitb automatically configures the device for optimizec read and write operations. a command user interface (cui) serves as the interface between the system processor and interna operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuration operations. a block erase operation erases one of the device?s 64k-byte blocks typically within 0.3s (5v v,,, 12v vp,) independent of other blocks. each block can be independently erased 100,000 times (1.6 million block erases per device). block erase suspend mode allows system software to suspend block erase to read or write data from any other block. writing memory data is performed in byte increments typically within 6u.s (5v vcc, 12v vpp). byte write suspend mode enables the system to read data or execute code from any other flash memory array location. rev. 1.3
lhf08ch3 4 individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. block lock-bits gate block erase and byte write operations, while the master lock-bit jates block lock-bit modification. lock-bit zonfiguration operations (set block lock-bit, set master lock-bit, and clear block lock-bits zommands) set and cleared lock-bits. the status register indicates when the wsm?s block erase, byte write, or lock-bit configuration operation is iinished. the ry/by# output gives an additional indicator of jvsm activity by providing both a hardware signal of status (versus software polling) and status masking iinterrupt masking for background block erase, for mample). status polling using ry/by# minimizes 30th cpu overhead and system power consumption. jvhen low, ry/by# indicates that the wsm is 3erforming a block erase, byte write, or lock-bit zonfiguration. ry/by#-high indicates that the wsm is ,eady for a new command, block erase is suspended :and byte write is inactive), byte write is suspended, 3r the device is in deep power-down mode. the access time is 120 ns (tavav) over the commercial temperature range (0% to +70?(z) ant vc, supply voltage range of 4.5v-5.5v. at lower vcc voltages, the access times are 150 ns (3.ov-3.6v: and 170 ns (2.7v-3.6v). the automatic power savings (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical i,,, current is 1 ma at 5v v,,. when ce# and rp# pins are at v,,, the i,, cmos standby mode is enabled. when the rp# pin is a gnd, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (tphqv) is required from rp# switching high until outputs arc valid. likewise, the device has a wake time (t,,,,: from rp#-high until writes to the cui are recognized with rp# at gnd, the wsm is reset and the status register is cleared. the device is available in 40-lead tsop (thin smal outline package, 1.2 mm thick). pinout is shown ir figure 2. rev.1.0
sharp lhf08ch3 5 figure 1. block diagram 49 ale a17 a16 ais a14 an a12 ce# vcc vpp rp# 41 alo as 43 a7 a6 a5 a4 40-lead tsop standard pinout 1 omm x 20mm top view nc nc we# oe# ry/by# dq7 dq6 dq5 dq4 vcc gnd gnd dq3 dq2 dqi dqo z a2 a3 figure 2. tsop 40-lead pinout rev. 1.0
sharp r r lhf08ch3 6 i symbol a,-al 9 dqo-dq7 ce# rp# oe# we# ry/by# output vcc gnd nc type input t input/ output input input input input supply supply supply name and function address inputs: inputs for addresses during read and write operations. addresses are internally latched during a write cycle. data input/outputs: inputs data and commands during cui write cycles; outputs data during memory array, status register, and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. chip enable: activates the device?s control logic, input buffers, decoders, and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. reset/deep power-down: puts the device in deep power-down mode and resets internal automation. rp#-high enables normal operation. when driven low, rp# inhibits write operations which provides data protection during power transitions. exit from deep power-down sets the device to read array mode. rp# at v,, enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. rp#=v,, overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. block erase, byte write, or lock-bit configuration with vihcrp# sharp lhf08ch3 7 2 principles of operation the LH28F008SCT-L12 smartvoltage flash memory includes an on-chip wsm to manage block erase, byte write, and lock-bit configuration functions. it allows for: 100% ttl-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from deep power-down mode (see bus operations), the device defaults to read array mode. manipulation of external memory control pins allow array read, standby, and output disable operations. status register and identifier codes can be accessed through the cui independent of the v,, voltage. high voltage on v,, enables successful block erasure, byte writing, and lock-bit configuration. all functions associated with altering memory contents-block erase, byte write, lock-bit configuration, status, and identifier codes-are accessed via the cui and verified through the status register. commands are written using standard microprocessor write timings. the cui contents serve as input to the wsm, which controls the block erase, byte write, and lock-bit configuration. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification, and margining of data. addresses and data are internally latch during write cycles. writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. interface software that initiates and polls progress of block erase, byte write, and lock-bit configuration can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read or write data from any other block. byte write suspend allows system software to suspend a byte write to read data from any other flash memory array location. 2: 1 data protection fffff foooo effff eoow dffff do000 cffff coooo bffff boo00 affff aoow sffff 90000 8ffff 80000 7ffff 70000 6ffff 60000 sffff 50000 4ffff 40000 jffff 30000 pffff 20000 1 ffff 10000 offff figure 3. memory map depending on the application, the system designer may choose to make the v,, power supply switchable (available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired to v,,,,,z13. the device accommodates either design practice and encourages optimization of the processor-memory interface. when vpp~vpplk, memory contents cannot be altered. the cui, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to v,,. all write functions are disabled when vcc is below the write lockout voltage vlko or when rp# is at v,,. the device?s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations. rev.1.3
sharp lhf08ch3 8 3 bus operation the local cpu reads and writes flash memory in-system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read information can be read from any block, identifier codes, or status register independent of the v,, voltage. rp# can be at either v,, or v,,. the first task is to write the appropriate read mode command (read array, read identifier codes, or read status register) to the cui. upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. four control pins dictate the data flow in and out of the component: ce#, oe#, we#, and rp#. ce# and oe# must be driven active to obtain data at the outputs. ce# is the device selection control, and when active enables the selected memory device. oe# is the data output (dq,-dq,) control and when active drives the selected memory data onto the i/o bus. we# must be at v,, and rp# must be at v,, or v,,. figure 15 illustrates a read cycle. 3.2 output disable jvith oe# at a logic-high level (v,,), the device outputs are disabled. output pins dc+,-dq, are olaced in a high-impedance state. 3.3 standby ze# at a logic-high level (vi,) places the device in standby mode #which substantially reduces device lower consumption. dqc-dq, outputs are placed in i high-impedance state independent of oe#. if deselected during block erase, byte write, or lock-bit :onfiguration, the device continues functioning, and consuming active power until the operatior completes. 3.4 deep power-down rp# at v,, initiates the deep power-down mode. in read modes, rp#-low deselects the memory places output drivers in a high-impedance state ant turns off all internal circuits. rp# must be held low fo a minimum of 100 ns. time tphqv is required afte return from power-down until initial memory acces: outputs are valid. after this wake-up interval, norma operation is restored. the cui is reset to read array mode and status register is set to 80h. during block erase, configuration modes, ,?;~low~ritell o;bo~ck;+; operation. ry/by# remains low until the rese operation is complete. memory contents beins altered are no longer valid; the data may be partially erased or written. time tphwl is requirod after rpb goes to logic-high (v,,) before another command car be written. as with any automated device, it is important tc assert rp# during system reset. when the systen- comes out of reset, it expects to read from the flask memory. automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes. if a cpu resei occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. sharp?s flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. rev. 1.0
lhf08ch3 9 3.5 read identifier codes operation 3.6 write the read identifier codes operation outputs the manufacturer code, device code, block lock configuration codes for each block, and the master lock configuration code (see figure 4). using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. the block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting. writing commands to the cui enable reading 01 device data and identifier codes. they also control inspection and clearing of the status register. when vpp=vpphli2/3~ the cui additionally controls block erasure, byte write, and lock-bit configuration. the block erase command requires appropriate command data and an address within the block to 5s erased. the byte write command requires the command and address of the location to be written. set master and block lock-bit commands require ths command and address within the device (master lock) or block within the device (block lock) to be locked. the clear block lock-bits command requires the command and address within the device. fffff foo04 foo03 foo02 reserved for future implementation block 15 lock configuration code 100021 10001 10000 offff block 1 lock configuration code master lock configuration code 00002 t ----------------- block 0 lock configuration code l------------------------------------ 00001~ device code manufacturer code block (i figure 4. device identifier code memory map the cui does not occupy an addressable memory location. it is written when we# and ce# are active. the address and data needed to execute a commanc are latched on the rising edge of we# or ce# (whichever goes high first). standard microprocessor write timings are used. figures 16 and 17 illustrate we# and ce#-controlled write operations. 4 command definitions when the v,, voltage 5 v,,,,, read operations from the status register, identifier codes, or blocks are enabled. placing v,,,,,,, on v,, enables successful block erase, byte write and lock-bii configuration operations. device operations are selected by writing specific commands into the cui. table 4 defines these commands. l rpv i n
shari= lhf08ch3 10 mode read output disable table 3. bus operations notes rp# ce# oe# we# address vpp d&.-r ry/by# 1,2,3,8 vt or ?il ?il ?i, x x hh dout x 3 ?i, or vr# ?il ?i, ?1, x x high z x standby 3 ?i, or vhh ?i, x x x x high z x deep power-down 4 v,, x x x x x high z vn,, read identifier codes 8 ?i, or vhh ?il ?il vlh see figure 4 ? note 5 ?oh write 3,6,7,8 ?. or hh ?il ?i, ?il x x dln x ?4otes: i. refer to dc characteristics. when vpp lhf08ch3 us cycle second bus cycle , jdr(2) 1 data(?) oper(?) 1 addr12) 1 datat3) read array/reset 1 1 write 1 x 1 ffh command table 4. command definit bus cycles first b rea?d. notes ooer(l) 1 ad ions(g) 11 read identifier codes 1 22 i 4 i write i x i 90h i read i ia i id /i read status register clear status register block erase 2 1 2 write x 70h read x srd write x 50h 5 write ba 20h write ba doh 40h ii byte write 2 5,6 write wa l& write wa wd id byte write 1 5 write x boh i id byte write 1 5 write x doh resume set block lock-bit set master lock-bit clear block lock-bits notes: 1. bus operations are defined in table 3. 2. x=any valid address within the device. ia=ldentifier code address: see figure 4. 1 2 7 write ba 60h write ba olh 2 7 write x 60h write x flh 2 8 write x 60h write x doh ba=address within the block being erased or locked. wa=address of memory location to be written. 3. srd=data read from status register. see table 7 for a description of the status register bits. wd=data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id=data read from identifier codes. 4. following the read identifier codes command, read operations access manufacturer, device, block lock, and master lock codes. see section 4.2 for read identifier code data. 5. if the block is locked, rp# must be at v,, to enable block erase or byte write operations. attempts to issue a block erase or byte write to a locked block while rp# is v,,. 6. either 40h or 10h are recognized by the wsm as the byte write setup. 7. if the master lock-bit is set, rp# must be at v,, to set a block lock-bit. rp# must be at v,, to set the master lock-bit. if the master lock-bit is not set, a block lock-bit can be set while rp# is v,,. 8. if the master lock-bit is set, rp# must be at v,, to clear block lock-bits. the clear block lock-bits operation simultaneously clears all block lock-bits. if the master lock-bit is not set, the clear block lock-bits command can be done while rp# is vi,. 9. commands other than those shown above are reserved by sharp for future device implementations and should not be used. rev. 1.0
lhfosch3 12 4.1 read array command 4.3 read status register command upon initial device power-up and after exit from deep dower-down mode, the device defaults to read array node. this operation is also initiated by writing the read array command. the device remains enabled ?or reads until another command is written. once the nternal wsm has started a block erase, byte write or ock-bit configuration, the device will not recognize :he read array command until the wsm completes ts operation unless the wsm is suspended via an erase suspend or byte write suspend command. the read array command functions independently of :he v,, voltage and rp# can be vi, or v,,. 4.2 read identifier codes command the identifier code operation is initiated by writing the qead identifier codes command. following the :ommand write, read cycles from addresses shown in =igure 4 retrieve the manufacturer, device, block lock :onfiguration and master lock configuration codes see table 5 for identifier code values). to terminate :he operation, write another valid command. like the ?ead array command, the read identifier codes :ommand functions independently of the v,, voltage lnd rp# can be v,, or v,,. following the read dentifier codes command, the following information :an be read: table 5. identifier codes *block is unlocked @block is locked *reserved for future use master lock configuration *device is unlocked odevice is locked *reserved for future use 4ote: . x selects the specific block lock configuration code to be read. see figure 4 for the device identifier code memory map. the status register may be read to determine when e block erase, byte write, or lock-bit configuration i: complete and whether the operation completec successfully. it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations outpu data from the status register until another valic command is written. the status register contents are latched on the falling edge of oe# or ce#, whichever occurs. oe# or ce# must toggle to vi, before further reads to update the status register latch. the reac status register command functions independently o? the v,, voltage. rp# can be v,, or v,,. 4.4 clear status register command status register bits sr.5, sr.4, sr.3, and sr.l are set to ?1?s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 7). by allowing system software to reset these bits, severa operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence: may be performed. the status register may be pollee to determine if an error occurre during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied v,, voltage. rp# can be vi, or v,,. this command is not functional during block erase or byte write suspend modes. 4.5 block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by an block erase confirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 5). the cpu can detect block erase completion by analyzing the output data of the ry/by# pin or status register bit sr.7. rev. 1.0
lhf08ch3 13 when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to ?1 ?i. also, reliable block erasure can only occur when vcc=vcc2,s and vpp=vpph1,2,3. in the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while v,,iv,,,k, sr.3 and sr.5 will be set to ?1 ?i. successful block erase requires that the corresponding block lock-bit be cleared or, if set, that rp#=v,,. if block erase is attempted when the corresponding block lock-bit is set and rp#=v,,, sr.l and sr.5 will be set to ?1?. block erase operations with v,, sharp lhf08ch3 14 4.8 byte write suspend command the byte write suspend command allows byte write interruption to read data in other flash memory locations. once the byte write process starts, writing the byte write suspend command requests that the wsm suspend the byte write sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the byte write suspend command is written. polling status register bits 33.7 and sr.2 can determine when the byte write operation has been suspended (both will be set to ?1?). ry/by# will also transition to v,,. specification t,,,,, defines the byte write suspend latency. at this point, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while dyte write is suspended are read status register and byte write resume. after byte write resume :ommand is written to the flash memory, the wsm nili continue the byte write process. status register 3ts sr.2 and sr.7 will automatically clear and :;;ize wi;o;;;;dto v,,. 4fter thethydrv;;z is wntten, automatically outputs status register data when read :see figure 8). v,, must remain at v,,,,,,,, (the same v,, level used for byte write) while in byte write suspend mode. rp# must also remain at v,, or v,, :the same rp# level used for byte write). 1.9 set block and master lock-bit commands 4 flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a naster lock-bit. the block lock-bits gate program and erase operations while the master lock-bit gates ilock-lock bit modification. with the master lock-bit lot set, individual block lock-bits can be set using the jet block lock-bit command. the set master .ock-bit command, in conjunction with rp#=v,,, bets the master lock-bit. after the master lock-bit is ;et, subsequent setting of block lock-bits requires joth the set block lock-bit command and v,, on the rp# pin. see table 6 for a summary of hardwan and software write protection options. set block lock-bit and master lock-bit are executed b! a two-cycle command sequence. the set block o master lock-bit setup along with appropriate block o device address is written followed by either the se block lock-bit confirm (and an address within tht block to be locked) or the set master lock-bit confirn (and any device address). the wsm then control: the set lock-bit algorithm. after the sequence i: written, the device automatically outputs statu: register data when read (see figure 9). the cpu car detect the completion of the set lock-bit event b\ analyzing the ry/by# pin output or status register bi sr.7. when the set lock-bit operation is complete, status register bit sr.4 should be checked. if an error iz detected, the status register should be cleared. the cui will remain in read status register mode until i new command is issued. this two-step sequence of set-up followed bb execution ensures that lock-bits are not accidentall] set. an invalid set block or master lock-bil command will result in status register bits sr.4 ant sr.5 being set to ?1 ?i. also, reliable operations occui only when vcc=vcc2,3 and vpp=vpph,,2/3. in the absence of this high voltage, lock-bit contents are protected against alteration. a successful set block lock-bit operation requires thai the master lock-bit be cleared or, if the master lock-bit is set, that rp#=v,,. if it is attempted with the master lock-bit set and rp#=v,,, sr.l and sr.4 will be set to ?1? and the operation will fail. set block lock-bit operations while vihcrp#cv,, produce spurious results and should not be attempted. a successful set master lock-bit operation requires that rp#=v,,. if it is attempted with rp#=v,,, sr.l and sr.4 will be set to ?1? and the operation will fail. set master lock-bit operations with v,,crp# lhf08ch3 15 4.10 clear block lock-bits command i all set block lock-bits are cleared in parallel via the clear block lock-bits command. with the master lock-bit not set, block lock-bits can be cleared using only the clear block lock-bits command. if the master lock-bit is set, clearing block lock-bits requires both the clear block lock-bits command and v,, on the rp# pin. see table 6 for a summary of hardware and software write protection options. clear block lock-bits operation is executed by a two-cycle command sequence. a clear block lock-bits setup is first written. after the command is written, the device automatically outputs status register data when read (see figure 10). the cpu can detect completion of the clear block lock-bits event by analyzing the ry/by# pin output or status register bit sr.7. when the operation is complete, status register bit sr.5 should be checked. if a clear block lock-bit error is detected, the status register should be cleared. the cui will remain in read status register mode until another command is issued. 1 this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. an invalid clear block lock-bits command sequence will result in status register bits sr.4 and sr.5 being set to ?1 i?. also, a reliable clear block lock-bits operation can only occur when vcc=vcc2,s and vpp=vpph1,2,3. if a clear block lock-bits operation is attempted while v,,rv,,,,, sr.3 and sr.5 will be set to ?1?. in the absence of this high voltage, the block lock-bits content are protected against alteration. a successful clear block lock-bits operation requires that the master lock-bit is not set or, if the master lock-bit is set, that rp#=v,,. if it is attempted with the master lock-bit set and rp#=v,,, sr.l and sr.5 will be set to ?1? and the operation will fail. a clear block lock-bits operation with v,,crp#cv,, p reduce spurious results and should not be attempted. if a clear block lock-bits operation is aborted due to v,, or vcc transitioning out of valid range or rp# active transition, block lock-bit values are left in an undetermined state. a repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. once the master lock-bit is set, it cannot be cleared. table 6. write protection alternatives master block operation lock-bit lock-bit rp# effect block erase or 0 v,, or vhh block erase and byte write enabled byte write x 1 v,, block is locked. block erase and byte write disabled \i block lock-bit override. block erase and bvte write set block lock-bit - set master lock-bit clear block lock-bits - ?hh enabled x vih or vhh set block lock-bit enabled x v,, master lock-bit is set. set block lock-bit disabled vhh master lock-bit override. set block lock-bit enabled x v,, set master lock-bit disabled vr+ set master lock-bit enabled x v,, , or v,, clear block lock-bits enabled x v,h master lock-bit is set. clear block lock-bits disabled .,--1--l --i~m.rh -...-i- hl-- ?,--,l# --i _.i ?hh rvrasrer lock-~ uvernae. lrear diock lock-ms enabled / rev. 1.0
lhfosch3 .16 table 7. status register definition wsms 1 ess 1 eclbs ( bwslbs 1 vpps 1 bwss 1 dps r 7 6 5 4 3 2 1 0 notes: sr.7 = write state machine status check ry/by# or sr.7 to determine block erase, byte 1 = ready write, or lock-bit configuration completion. 0 = busy sr.6-0 are invalid while sr.7=?0?. sr.6 = erase suspend status if both sr.5 and sr.4 are ?1 ?s after a block erase or 1 = block erase suspended lock-bit configuration attempt, an improper command 0 = block erase in progress/completed sequence was entered. sr.5 = erase and clear lock-bits status sr.3 does not provide a continuous indication of v,, 1 = error in block erasure or clear lock-bits level. the wsm interrogates and indicates the v,, level 0 = successful block erase or clear lock-bits only after block erase, byte write, set block/master lock-bit, or clear block lock-bits command sequences. sr.4 = byte write and set lock-bit status sr.3 is not guaranteed to reports accurate feedback 1 = error in byte write or set master/block lock-bit 0 = successful byte write or set master/block only when v,,#v,,,,,,,,. lock-bit sr.l does not provide a continuous indication of master and block lock-bit values. the wsm interrogates the sr.3 = v,, status master lock-bit, block lock-bit, and rp# only after block 1 = v,, low detect, operation abort erase, byte write, or lock-bit configuration command 0 = v,, ok sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set, master sr.2 = byte write suspend status lock-bit is set, and/or rp# is not v,,. reading the block 1 = byte write suspended lock and master lock configuration codes after writing 0 = byte write in progress/completed the read identifier codes command indicates master and block lock-bit status. sr.1 = device protect status 1 = master lock-bit, block lock-bit and/or rp# lock sr.0 is reserved for future use and should be masked detected, operation abort out when polling the status register. 0 = unlock sr.0 = reserved for future enhancements
shari= lhfosch3 * read status bus operation command i commenk i i i i i write data=mh erase setup addr=wlthm block lo be erased i write ems.3 datedoh cotlfilll7 addr=within block to be erased read status register data i 1.,, check sr.7 iswsm ready o=wsm busy repeat for subsequent block erasures. full status check can be done after each block erase or alter a sequence of block erasures. write ffh after the last operation to place device i? read array mode. fullstatuscheckprocedure command i comments i standby check sr.3 l=vpp error detect standby check sr. 1 t&evice protect detect rp#=v,,,blwk lock-bit is set only required for systems implemenbng lock-bit configuration standby check sr.4.5 both t=command sequence error i i standby check sr.5 l=block erase error i i sr.s.sr.4.sr.3 and sr.l are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if error is detected. clear the status register before attempbng reby or other error recovery. figure 5. auiomatea uiock trase rlowcnan rev. 1.0
shari= lhfosch3 data and address suspend byte full status check procedure read status aeglster data(see above) deuce protect error byte write successful command comments write setup byte wnte data40h addr=location to be written data=data to be written write byte wnte ackfr=locabon to be written read status register data standby check sr.7 l=wsm ready o=wsm busy repeat for subsequent byte writes. sr full stat?s check can be done after each byte write, or after a sequence of byte writes. write ffh after the last byte write operahon to place device i? read array mode. bus operation command comments standby check sr.3 l=vpp error detect check sr. 1 standby l=devlce protect detect rp#=v,,+block lock-bit 1s set only requtred for systems implemenbng lock-bit configuration standby check sr.4 t=data wnte error sr.4sr.3 and six, are only cleared by the clear status register command in cases where multiple locations are written before full status is checked. if error is detected, clear the status regtster before attempting retry or other error recovery. figure 6. automated byte write flowchart rev. 1.0
sharp lhf08ch3 byte write loop bus operation command comments standby data=boh addr=x status regtster data addr=x check sr.7 l=wsm ready o=wsm busy standby check sr.6 l=block erase suspended o&lock erase completed write data=doh addr=x figure 7. block erase suspend/resume flowchart rev.1.0
lhf08ch3 w sr.7= 0 1 sr.z= 0 byte write completed c 1 bus 0per&l0ll command comments write byte write suspend data&oh addr=x read status register data addr=x standby standby i---- check sr.7 l=wsm ready o=wsm busy check sr.2 t=byte write suspended 04yte write completed read read array locations othel than that being written. figure 8. byte write suspend/resume flowchart
lhf08ch3 21 block/dewce address block/device address f read status register 1::3 0 sr.7= 1 check if desired pull status check procedure read status register data(see above) bus operation write write read standby command set block/master lock-bit setup set block or master lock-bit confirm t data&oh addr=blcck address(biock). dewce address(master) data=olh(block), flh(master) addr=btock address(block). dewce address(master) status register data check sr.7 l=wsm ready o=wsm busy qepeat for subsequent lock-bit set operations. %ll status check can be done after each lock-bit set operahon or after a sequence of lock-bit set operations. wnte ffh after the last lock-bit set operatmn to place dewce i? read array mode. bus operation command standby standby comments check sr.3 l=vpp error detect check sr.l l=dewce protect detect rp#=v,, (set master lock-en operation) rp#=vih, master lock-bit is set (set block lock-blt operation) check sr.4.5 both l=command sequence error check sr.4 t=set lock-bit error srs,sr.4.sr.3 and sr., are only cleared by the clear status register command iii cases where multiple lock-bits are set before full status is checked. if error is detected, clear the status register before attempting retry or other error reccweiy. figure 9. set block and master lock-bit flowchart rpv 1 n
. sharp full status check procedure device protect error command sequence error clear block lock-bits error lhf08ch3 22 bus operation command comments write write clear block lock-bits setup clear block lock-bits confirm data=goh addr=x data=doh addr=x read standby status register data check sr.7 l=wsm ready a;wsm busy write ffh after the clear block lock-bits operation to place device i? read array mode. bus operation standby command comments check sr.3 l=vpp error detect standby check sr. 1 l=device protect detect rp#=+, master lock-bit 1s set standby check sr.4.5 both l=command sequence error standby check sr.5 l&lea block lock-bits error 3r.s.sr.4.sr.3 and sr.l are oniy cleared by the clear status register command. i f error is detected, clear the status register before attempting retry or other error recovely. l figure 10. clear block lock-bits flowchart rev. 1.0
lhf08ch3 23 5 design considerations 5.1 three-line output control the device will often be used in large memory arrays. sharp provides three control inputs to accommodate multiple memory connections. three-line control provides for: a. lowest possible memory power dissipation. b. complete assurance that data bus contention will not occur. to use these control inputs efficiently, an address decoder should enable ce# while oe# should be connected to all memory devices and the system?s read# control line. this assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 5.2 ry/by# and block erase, byte write, and lock-bit configuration polling ry/by# is a full cmos output that provides a hardware method of detecting block erase, byte write and lock-bit configuration completion. it transitions low after block erase, byte write, or lock-bit configuration commands and returns to voh when the wsm has finished executing the internal slgorithm. ry/by# can be connected to an interrupt input of the system cpu or controller. it is active at all times. ry/by# is also voh when the device is in block erase suspend (with byte write inactive), byte write suspend or deep power-down modes. 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers arc interested in three supply current issues; standb current levels, active current levels and transien peaks produced by falling and rising edges of cei and oe#. transient current magnitudes depend oi the device outputs? capacitive and inductive loading two-line control and proper decoupling capacito selection will suppress transient voltage peaks. eacl device should have a 0.1 pf ceramic capacito connected between its v,, and gnd and between it: v,, and gnd. these high-frequency, low inductance capacitors should be placed as close as possible tc package leads. additionally, for every eight devices a 4.7 pf electrolytic capacitor should be placed at thf array?s power supply connection between v,, ant gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.4 vpp trace on printed circuit boards updating flash memories that reside in the targe system requires that the printed circuit boarc designer pay attention to the v,, power supply trace the v,, pin supplies the memory cell current for byte writing and block erasing. use similar trace width: and layout considerations given to the v,, powel bus. adequate v,, supply traces and decoupling wil decrease v,, voltage spikes and overshoots. rev. 1.0
si-iarp lhf08ch3 24 5.5 vcc, vpp, rp# transitions block erase, byte write and lock-bit configuration are not guaranteed if v,, falls outside of a valid vpph,,z3 range, v,, falls outside of a valid vcc,,s range, or rp##v,h or v,,. if v,, error is detected, status register bit sr.3 is set to ?1? along with sr.4 or sr.5, depending on the attempted operation. if rp# transitions to v,, during block erase, byte write, or lock-bit configuration, ry/by# will remain low until the reset operation is complete. then, the operation will abort and the device will enter deep power-down. the aborted operation may leave data partially altered. therefore, the command sequence must be repeated after normal operation is restored. device power-off or rp# transitions to v,, clear the status register. the cui latches commands issued by system software and is not altered by v,, or ce# transitions or wsm actions. its state is read array mode upon dower-up, after exit from deep power-down or after vcc transitions below v,,,. after block erase, byte write, or lock-bit configuration, 3ven after v,, transitions down to v,,,,, the cui must be placed in read array mode via the read 4rray command if subsequent access to the memory array is desired. 5.6 power-up/down protection the device is designed to offer protection against sccidental block erasure, byte writing, or lock-bit :onfiguration during power transitions. upon lower-up, the device is indifferent as to which power supply (v,, or vcc) powers-up first. internal circuitry resets the cui to read array mode at power-up. a system designer must guard against spuriou writes for v,, voltages above vlko when v,, i! active. since both we# and ce# must be low for ( command write, driving either to v,, will inhibit writes the cul?s two-step command sequence architectun provides added level of protection against datz alteration. in-system block lock and unlock capability prevent! inadvertent data alteration. the device is disablec while rp#=v,, regardless of its control inputs state. 5.7 power dissipation when designing portable systems, designers mus consider battery power consumption not only during device operation, but also for data retention during system idle time. flash memory?s nonvolatilio increases usable battery life because data is retainec when system power is removed. in addition, deep power-down mode ensures extremely low power consumption.even when systerr power is applied. for example, portable computing products and other power sensitive applications tha, use an array of devices for solid-state storage car consume negligible power by lowering rp# to vi, standby or sleep modes. if access is again needed the devices can be read following the tphqv ant t,,,, wake-up cycles required after rp# is firs! raised to v,,. see ac characteristics- read only and write operations and figures 15, 16 and 17 for more information. rev. 1.0
si-iarp lhf08ch3 25 6 electrical specifications 6.1 absolute maximum ratings* operating temperature during read, block erase, byte write and lock-bit configuration . . . . . . . . . . . 0c to +70x(?) temperature under bias . . . . . . . . . . . . . . . -10c to +8o?c storage temperature _....................... -65c to +125?c voltage on any pin (except v,,, v,,, and rp#) . . . . . . . -2.ov to +7.0vt2) v,, supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -2.ov to +7.ov(2) v,, update voltage during block erase, byte write and lock-bit configuration . . . . . . . . . . . -2.ov to +14.0v(2v3) rp# voltage with respect to gnd during lock-bit configuration operations . . . . . . -2.ov to +14.0v(293) output short circuit current . . . . . . . . . . . . . . . . . . . . . . . . 1 00ma(4) *warning: stressing the device beyond tht ?absolute maximum ratings? may cause permanen damage. these are stress ratings only. operation beyond the ?operating conditions? is no recommended and extended exposure beyond the ?operating conditions? may affect device reliability. notes: 1. operating temperature is for commercia temperature product defined by this specification. 2. all specified voltages are with respect to gnd minimum dc voltage is -09 on input/output pin: and -0.2v on vcc and v,, pins. during transitions, this level may undershoot to -2.ov fol periods c20ns. maximum dc voltage or input/output pins and v,, is vcc+osv which during transitions, may overshoot to vc.c+2.0v fol periods <20ns. 3. maximum dc voltage on v,, and rp# ma) overshoot to +14.ov for periods <20ns. 4. output shorted for no more than one second. nc more than one output shorted at a time. 5.2 operating conditions iote: . block erase, byte write and lock-bit configuration operations with vccc3.ov should not be attempted. i.2.1 capacitance(?) t/,=+25%, f=l mhz symbol parameter typ. max. unit condition c,n input capacitance 6 8 pf v,,=o.ov cn, ,t output capacitance 8 12 pf vn, ,,=o.ov sote: . sampled, not 100% tested. rev. 1.2
sharp lhf08ch3 26 2.2 ac input/output test conditions ~~~~~~)(~ ac test inputs are driven at 2.7v for a logic ?1? and o.ov for a logic ?0.? input timing begins, and output timing ends, at 1.35v. input rise and fall times (10% to 90%) sharp lhf08ch3 27 i.2.3 dc characteristics dc characteristics vcc=2.7v 1 vcc=3.3v notes typ. 1 max. 1 typ. 1 max. test conditions v,,=v,,max. vin=vct: or gnd sym. ?li parameter input load current output leakage curreni v,, standby current &l cia 210 pa 25 100 pa 0.4 2 ma 10 pa 17 35 ma / ?lo t 100 20 100 ff 2 0.2 2 cmos inputs ?cc, ?ccd vcc=vccmax. ce#=rp#=v,,+0,2v ttl lnouts vcc=vccmax. ce#=rp#=v,,, rp#=gnd*0.2v ini ,,(ry/by#)=oma cmos inputs vcc=vccmax. ce#=gnd f=5mhz(3.3v, 2.7v), ? 8mhz(5v) ini it=oma ttl inputs vcc=vccmax. ce#=gnd f=5mhz(3.3v, 2.7v), 8mhz(5v) h&dnep power-down v,, read current 1,5,6 1 ?cc, ccw cce ccws pps ppr ppd ppw 12 7 12 i-t 18 8 18 20 50 ma * - 17 - 17 ?3 - 12 - 1-i - li t - 12 - 1 6 in, ,,=oma j,+3.3v+o.3v jpp=12.0v+0.6v jpp=3.3v?0.3v jpp=5.ov+o.5v jpp=12.0v&0.6v 3e#=v,, \ \ \ \ \ \ ( \ \ e \ \ \ \ \ \ \ j,,vcr. qp#=gnd,0.2v jpp=3.3v*0.3v jpp=5.0v+o.5v jpp=12.0v+0.6v jod=3.3v*o.3v - - ma 35 ma 30 ma - - ma 30 ma 25 ma 1 10 ma & *15 pa 10 200 pa 0.1 5 pa j,, byte write or jet lock-bit current \ : \ ( ( \ e \ ( \ ( \ 1 \ ( \ j 1,7 - - -f - 12 - j,, block erase or zlear block lock-bits hrrent j,, byte write or block erase suspend current /pp standby or read hrrent /pp deep power-down hrrent /pp byte write or set -ock-bit current 1 *2 10 d= 1 0.1 1,7 - +15 -c2 -cl5 200 10 200 ~ 5 0.1 5 - 40 - 40 - 15 - 20 - t- - 1.7 /pp block erase or zlear lock-bit current ppe ppws ppfs - 20 - i 15 - 10 200 - ---i= - 1 /pp byte write or block irase suspend current 10 1 200 1 pa i - i i i i rev. 1.3
sharp lhf08ch3 dc characteristics (continued) vcc=2.7v v,,=3.3v vc,=5v test sym. parameter notes min. max. min. max. min. max. unit conditions v,, input low voltage 7 -0.5 0.8 -0.5 0.8 -0.5 0.8 v vi, input high voltage 7 2.0 vcc 2 0 +0.5 . vcc 2.0 +0.5 vcc v +0.5 vol output low voltage 3,7 vcc=vccmin. 0.4 0.4 0.45 v lol=5.8ma(vcc=5v) lol=2.0ma (vcc=3.3v, 2.7v) voh, output high voltage 3,7 vcc=vccmin. vw 2.4 2.4 2.4 v lo,=-2.5ma(vcc=5v) lo,=-2.0ma(vcc=3.3v) lnh=-1 .5ma(v,,=2.7v) voh2 output high voltage 3,7 0.85 0.85 0.85 (cmos) vnc vcc v vcc=vccmin. vnr. in,=-2.0ma vcc !$,c vcc -0.4 -0.4 v - ;c?yococm;n. ij v,,,, v,, lockout during 497 normal operations 1.5 1.5 1.5 v v,,,,, v,, during byte write, block erase or - - 3.0 3.6 - - v lock-bit operations vpph2 v,, during byte write, block erase or - - 4.5 5.5 4.5 5.5 v lock-bit operations v,,,, v,, during byte write, block erase or - - 11.4 12.6 11.4 12.6 v lock-bit operations v, kn vcr: lockout voltage 2.0 2.0 2.0 v ?hh rp# unlock voltage 8,9 set master lock-bit - - 11.4 12.6 11.4 12.6 v override master and block lock-bit notes: 1. all currents are in rms unless otherwise noted. typical values at nominal v,, voltage and ta=+25?c. 2* ?ccws and ?cc,, are specified with the device de-selected. if read or byte written while in erase suspend mode, the device?s current draw is the sum of lccws or icces and lccr or i,,,, respectively. 3. includes ry/by#. 4. block erases, byte writes, and lock-bit configurations are inhibited when v,, lhfosch3 6.2.4 ac characteristics - read-only operations(?) vc,=2.7v-3.6v, tpo?c to +70x versiond4) lh28f008sgl170 sym. 1 parameter 1 notes min. max. unit 1 read cycle time 170 ns see 5.ov v,, read-only operations for notes 1 through 4. vc,=3.3v&0.3v, t versiond4) ,=o?c to +70x 1 parameter 1 notes ( lh28foossgl150 min. max. sym. 1 unit t*?n? read cycle time 150 ns ta?n? address to output delay 150 ns ff, 0? ce# to output delay 2 150 ns tph()? rp# high to output delay 600 ns tr, 0" oe# to output delay 2 55 ns hny ce# to output in low z 3 0 ns t&jq7 ce# high to output in high z 3 55 ns : in low z 3 0 ns tr,, nx oe# to output tncln7 oe# high to output in high z 3 25 ns bh output hold from address, ce# or oe# change, whichever occurs first 3 0 ns note: see 5.ov v,, read-only operations for notes 1 through 4. rev. 1.0
shari= lhf08ch3 notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe# may be delayed up to t elqv-blqv after the falling edge of ce# without impact on telov. 3. sampled, not 100% tested. 4. see ordering information for device speeds (valid operational combinations). rev. 1.0
sliarp lhf08ch3 device data valid . ..i..#... address stable 4- tavav b vih ce#(e) vil vih oe#(g) vil ,,,,.,..i. vih . ..#...i.. we#(w) vil voh data( d/q) (dqo-dq7) vol vcc tphqv vih t rp#(p) vil ?????7 figure 15. ac waveform for read operations rpv 1 n
lhf08ch3 32 6.2.5 ac characteristics - write operation(?) vc,=2.7v-3.t version&) ,=o?c to +7o?c lh28f008sgli 70 sym. 1 _ __-.-_.- parameter :ovety to we# going low notes min. 170 max. unit ns note: see 5.ov v,, we#-controlled writes for notes 1 through 5. sym. 1 vc,=3.3v+0.3v, ta=o?c to +7o?c versions@) parameter 1 notes lh28f008sgl150 min. max. unit note: see 5v v,, ac characteristics - write operations for notes 1 through 5. rev. 1.2
sliari= lhf08ch3 33 v(-.,=sv*o.s\ versiat@) j, t,=o?c to +70x __._. -.._ lh28f008sgl120 sym. ( parameter 1 notes min. max. unit tavnv ( write cycle time 120 ns 1. read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as during read-onry operations. refer to ac characteri! sties for read-only operations. 2. sampled, not 100% tested. 3. refer to table 4 for valid a,, and din for block erase, byte write, or lock-bit configuration. 4. v,, should be held at v,,h,12,3 ( and if necessary rp# should be held at v,,) until determination of block erase, byte write, or lock-bit configuration success (sr.1/3/4/5=0). 5. see ordering information for device speeds (valid operational combinations). notes: rpv 13
shari= lhf08ch3 addresses(a) ce#(e) oh(g) data(d/q) ry/by#(r) rp#(p) 1 2 3 6-0 vih vil vih vil vih vhh vih - notes: 1. vcc power-up and standby. 2. write block erase or byte write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. figure 16. ac waveform for we#-controlled write operations rev. 1.0
lhf08ch3 6.2.6 alternative ce#-controlled writes(?) i c vcc:=2.7v-3.f iv, t,,= :o?c to +7o?c vetgods) -~ _.-.~- i lh28foossgli 70 - ..--_ ----- -_.- i i sm. i parameter 1 notes 1 min. i max. i unit ii ta?*? write cycle time 170 ix tphf, rp# high recovery to ce# going low 2 1 is t we# setuo to ce# goina low c-l ns wi i high i to ce# going high ?ram ce# high 70 ns 3 50 ns 1 50 i ns 5 t ns note: e# high n ce# high dth high fror wit very before read 5 ns 0 ns 25 ns 0 i ns see 5.ov vc-. alternative ce#-controlled writes for notes 1 through 5. i, sym. 1 wc,=3.3v+0.3v, t,po?c to +7o?c versions@) lh28foossgl150 parameter 1 notes 1 min. max. unit 1 write cycle time tfhrl 1 ce# high to r tfhnl 1 write recovery before read ----i- ---1 -~--b- ns 1 vpp hold from valid srd, ry/by# high rp# vhh hold from valid srd, ry/by# high i 2,4 i 0 ns i 2,4 0 ns 1 note: see 5v vcc alternative ce#-controlled writes for notes 1 through 5. rev. 7.0
sharp lhf08ch3 sym. 1 _ -_-_ -._- parameter vo,=5vio.5 versiansw v, tpo?c to +7o?c 1 notes 1 lh28f008sgl120 min. max. unit 1 b 1 write cycle time 120 ns i 50 ns ii tphf, rp# high recovery to ce# going low 2 1 pi tw, i-, we# setup to ce# going low i 0 ns tr, pc( ce# pulse width hfh rp# v,,,, setup to ce# going high 2 100 ns ing high 2 100 ns high 3 40 ns t?pfh vp,, setup to ce# go fl\?f, i address setup to ce# going , tn?fh data setup to ce# going hig ih 3 40 ns ii tfhnx 1 data hold frr- re* uinh i i e i i cl.2 i tfhnx 1 address hoi ? ll?lll ulir r ,kjl, i i i i i13 t we# hold from ce# hiah ns i tfhg, write recovery before read 0 ns ?2vvl vpp hold from valid srd, ry/by# high 2,4 0 ns bvph rp# vhh hold from valid srd, ry/by# high 2,4 0 ns notes: 1. in systems where ce# defines the write pulse width (within a longer we# timing waveform), all setup, hold, and inactive we# times should be measured relative to the ce# waveform. 2. sampled, not 100% tested. 3. refer to table 4 for valid a,, and dl, for block erase, byte write, or lock-bit configuration. 4. v,, should be held at v,,,,,z,s ( and if necessary rp# should be held at v,,) until determination of block erase, byte write, or lock-bit configuration success (sr.1/3/4/5=0). 5. see ordering information for device speeds (valid operational combinations). rev. 1.0
lhf08ch3 r addresses(a) we#(w) oe#(g) ce#(e) data(d/q) rp#(p) -- -- -- -- vih tehax vih tehgl vih i i i vhh vih -- notes: 1. vcc power-up and standby. 2. write block erase or byte write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. figure 17. ac waveform for ce#-controlled write operations rev. 1.0
sharp lhf08ch3 38 6.2.7 reset operations ?ijh ~~ ry/by#( r) vol vih rp#(p) vil (a)reset during read array mode voh ry/by#(r) vol vih rp#(p) vil (b)reset during block erase, byte write, or lock-bit configuretion 2.7vl3.3vl5v t vcc vil - b35vph 2 vih rp#(p) ! vil 7 (c)rp# rising timing figure 18. ac waveform for reset operation sym. tplph tplrh t235vph i ?jotes: 2 : i. if rp# is asserted while a block erase, byte write, or lock-bit configuration operation is not executing, the reset will complete within 1 oons. !. a reset time, tphqv, is required from the latter of ry/by# or rp# going high until outputs are valid. 3. when the device power-up, holding rp# low minimum 100ns is required after vcc has been in predefined range and also has been in stable there. rev. 1.3
lhf08ch3 5.2.8 block erase, byte write and lock-bit configuration performance(3y4) t whqvs set lock-bit time 2 12 150 10 100 tfhn?2 lj= t whqv4 ffh()?4 clear block lock-bits time 2 1.1 5 1 4 s twhrh1 byte write suspend latency time to 7.5 ~ read 5.6 7 5.2 lj= iwhrh2 erase suspend latency time to read 9.4 13.1 9.8 12.6 i.= fhrh7 ?4otes: i. typical values measured at ta=+25?c and nominal voltages. assumes corresponding lock-bits are not set. subject to change based on device characterization. !. excludes system-level overhead. 3. sampled but not 100% tested. i. block erase, byte write and lock-bit configuration operations with vccc3.ov and/or vppc3.0v are not guaranteed. rev. 1.3
lhf08ch3 40 7 additional information 7.1 ordering information product line designator for all sharp flash products i i i ~l~h/2181f10~0~8/sic~(h~t/ -il/l 121 l device density 008 = b-mbit architecture s = regular block power supply type c = smartvoltage technology operating temperature] blank = 0c - +7o?c - h = -40c - +85?c _ i l i aczs speed (ns) 85:85ns(5v,30pf), 90ns(5v), 120ns(3.3v), 150ns(2.7v) 12:120ns(5v), 150ns(3.3v) 170ns(2.7v) package t = 40-lead tsop r = 40-lead tsop(reverse bend) n = 44-lead psop b = 42 or 48-ball csp valid operational combinations v,,=2.7-3.6v v,p3.3+0.3v v,,=5.0*0.5v 5opf load, 5opf load, 1 oopf load, option order code 1.35v i/o levels 1.5v i/o levels ttl l/o levels 1 l!-l28f008sct-l12 lh28f008sc-l170 lh28f008sc-l1.50 lh28f008sc-l120 rev. 1.0
sharp lhfosch3 41 8 package and packing specification ) 1. package outline specification refer to drawing no.aal 10 5 2. markings 2 - 1. marking contents ( 1 ) product name : lh28f008sct-l ( 2 ) company name : sharp ( 3 ) date code (example) 12 yy ww xxx indicates the product was manufactured (01,02,03, * - - * * 52,53) - denotes the product ion year. (lower two digit of the year.) - denotes the product ion ref.code c> (no marking , a , b , (4) ?japan? is marked on the package when both wafer and assemb done in japan , indicating the country of origin. 2-2. marking layout ly processes are refer drawing no.aal 10 5 (this layout does not define the dimensions of marking character and marking position.) 3. packing specification (dry packing for surface mount packages) dry packing is used for the purpose of maintaining ic quality after mounting packages on the pcb (printed circuit board). when the epoxy resin which is used for plastic packages is stored at high humidity, it may absorb 0.15% or more of its weight in moisture. if the surface mount type package for a relatively large chip absorbs a large amount of moisture between the epoxy resin and insert material (e.g. chip, lead frame) this moisture may suddenly vaporize into steam when the entire package is heated during the soldering process (e.g. vps). this causes expansion and results in separation between the resin and insert material, and sometimes cracking of the package. this dry packing is designed to prevent the above problem from occurring in surface mount packages. 3 - 1 . packing materials material name material specificaiton purpose tray conductive plastic (50devices/tray) fixing of device upper cover tray conductive plastic (ltray/case) fixing of device _-__________----_-__~~~----.--~~~.~..~--.~~---------~~~-~-.----~~~~~~~-~~-------...~~.~.~~~~~~~....~.~~~~~.....~~~-~...~~~~~--.-~~~~~------~~~~~..~~~~~~........ laminated aluminum bag aluminum polyethylene (lbag/case) drying of device .__-.-._-__......_-_~~~...........~~~~...........-..--..---~~---~....~~~~-...-~~~~~----~-~~~...~-~~~......-----.~....-~~~~~~~ desiccant silica gel drying of device _....._--_---___......--~~.~.~......-~..-.--~~~~....~--~~~~~~........--~~~~~~~~.--...............~~.~.......~~.-..-~~~-------~~...~---~.....-..---.....--------- p p band polypropylene (3pcs/case) fixing of tray _____._-_----..-____..------~~.......~~~~.----~~~~~~~~----.~~~~~~.~~.--------~~-~~~~~~~~~~.~~.....~~~~~.....~.~~.-.~.~~~~------~~~~---.~~.~...----~.....-.------ inner case card board (500devices/case) packaging of device _______-.-.....-____..---~--~~.......~-~~.~.------~.~~~---.------~--.--~.---..-....................~.... _......._.__......__~.~~~~.~~..~~~~~.....~~~~~....~...~ label paper indicates part number, quantity and date of manufacture outer case card board outer packing of tray (devices shall be placed into a tray in the same direction.)
sharp lhf08ch3 42 1 3-2. outline dimension of tray refer to attached drawing ing t he dry packing 4. storage and opening of dry packing 4-l. store under conditions shown below before open (1) temperature range : 5-40c (2) humidity : 80% rh or less 4 - 2. notes on opening the dry packing (1) before opening the dry packing, prepare a working table which is grounded against esd and use a grounding strap. (2) the tray has been treated to be conductive or anti-static. if the device is transferred to another tray, use a equivalent tray. 4 - 3. storage after opening the dry packing perform the following to prevent absorption of moisture after opening. ( 1) after opening the dry packing, store the ics in an environment with a and temperature of 5--25c and a relative humidity of 60% or less mount ics within 72 hours after opening dry packing. 4 - 4. baking (drying) before mounting (1) baking is necessary (a) if the humidity indicator in the desiccant becomes pink (b) if the procedure in section 4-3 could not be performed ( 2) recommended baking conditions if the above conditions (a) and (b) are applicable, bake it be mounting. the recommended conditions are 16-24 hours at 120c. heat resistance tray is used for shipping tray. fore 5. surface mount conditions please perform the following conditions when mounting ics not to deteriorate ic quality. 5-l .soldering conditions(the following conditions are valid only for one time soldering.) 1 mounting method reflow solder ing (air) manual soldering (soldering iron) temperature and duration peak temperature of 230c or less, duration of less than 15 seconds. 200c or over,durat ion of less than 40 seconds. temperature increase rate of i--4?c/second 260c or less, duration of less than 10 seconds. measurement point ic package surface ic outer lead surface 5-2. conditions for removal of residual flux ( 1) ultrasonic washing power : 25 watts/liter or less (2) washing time : total 1 minute maximum (3) solvent temperature : 15-40c
sharp lhf08ch3 43 i gi lh28foo8sct-l12 i-l n d i z isee detail a ____ detail a pkg.base plane :cez : uj apan ~~&&%6$$&0?--3{~& notes : marking specification when ?japan" is marked. ml; ii - r;?lkk. \ tin-leac .$%% -95x$7 3~~s~-9fi#?rir;l~, /u @%8vf@!%i ., name : tsop40-p-1020 lead finish i plating note plastic body dimensions do not include burr of resin. drawing no. j aa1105 @(il ; unit / mm
stiarl= lhf08ch3 pkg .dase pt. ane i 18. 4+0. 2 /see detail a detail a p&-g2 : 5 j ap anfl ~%wz?t%j@~-?- 3tt#% notes : marking specification when ?japan? is not marked. lame [ tsop40-p-1020 lead finish ; plating note plastic body dimensions do not include burr g-i2 / of resin. drawing no. i aa1105 unit j mm
sharp lhf08ch3 4 - 3 , : c 1 - .o - ( a- - _ - . j i i j ) i i i ) i $33 1 tic% iame;tsop40-lozotcm-rh note stiz j drawing no. 1 cv644 unit ! mm
shari= lhf08ch3 46 (supplementary data) lhf08ch3 recommended mounting conditions for two time reflow soldering . product name(package) LH28F008SCT-L12(ts0p40-p-1020) packing specification tray (dry packing) wount ing method reflow soldering (air) reflow soldering conditions peak temperature of 230c or less. 200c or over, duration of less than 40 seconds. preheat temperature of 1?25-150?c,duration of less than 180 seconds. temperature increase rate of l--4?c/second. measurement point ic package surface storage conditions after opening the dry packing, store the ics in an environment with a temperature of 5--25c and a relative humidity of 60% or less. if doing reflow soldering twice,do the first reflow soldering within 72 hours after opening dry packing and do the second reflow soldering within 72 hours after the first reflow soldering. note if the above storage conditions are not applicable, bake it before reflow soldering. the recommended conditions are 16-24 hours at 120c. (heat resistance tray is used for shipping tray.) recommended reflow soldering(air) temperature profile peak temoe rature temperaturi increase rate 1 -4?c/second (no. 990414-x11)
sharp lhf08ch3 47 flash memory lhfxxcxx family data protection noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. such noises, when induced onto web signal or power supply, may be interpreted as false commands, causing undesired memory updating. to protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1) protecting data in specific block when a lock bit is set, the corresponding block is protected against overwriting. by using this feature, the flash memory space can be divided into the program section(locked section) and data section(unlocked section). the master lock bit can be used to prevent false block bit setting. by controlling rp$, desired blocks can be locked/unlocked through the software. for further information on setting/resetting block bit and controlling of iq?%, refer to the spec i f icat ion. (see chapter 4.9 and 4.10) 2) data protection through vpp when the level of vpp is lower than vpplk (lockout voltage), write operation on the flashmemory is disabled. allblocksare lockedandthedata intheblocksarecompletely write protected. for the iockout voltage, refer to the specification. (see chapter 6.2.3.) 3) data protection through rp# when the rp# is kept low during power up and power down sequence such as voltage transition, write operation on the flash memory is disabled, write protecting all blocks. for the details of rp# control, refer to the specifi cat ion. (see chapter 5.6 and 6.27. > rev 1.3

▲Up To Search▲

Price & Availability of LH28F008SCT-L12

	To Download LH28F008SCT-L12 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .